Microprocessors typically function by executing a series of instructions organized in a program. Microprocessors are referred to hereinafter as processors. A processor may execute an instruction over one or more clock cycles. To increase the execution of instructions, some processors concurrently execute one or more instructions. The z/Architecture Principles of Operations, (SA22-7832-09) published September, 2012 by IBM and incorporated by reference herein in its entirety teaches an example instruction set architecture (ISA).
For example, a first and second instruction may be executed concurrently if the second instruction is not dependent on the first instruction. As a result, some sequential instruction groups may be difficult to execute concurrently. As a result, modern processors often execute instructions out of order to increase throughput, concurrently processing unrelated instructions.
In addition, modern processors may be configured to execute more than one instruction per clock cycle. Thus a first instruction may be executed while a later third instruction is executed out of order, followed by the execution of a second instruction.
Unfortunately, it is more difficult to issue multiple instructions. Issuing and executing multiple instructions per cycle requires significant hardware support to track and resolve dependencies, with the hardware requirements typically increasing with the square of the number of execution units.
U.S. Pat. No. 6,609,190 titled “Microprocessor with primary and secondary issue queue” by James Allan Kahle et. al, and assigned to IBM, filed Jan. 6, 2000 teaches a processor and data processing system suitable for dispatching an instruction to an issue unit. The issue unit includes a primary issue queue and a secondary issue queue. The instruction is stored in the primary issue queue if the instruction is currently eligible to issue for execution. The instruction is stored in the secondary issue queue if the instruction is currently ineligible to issue for execution. An instruction may be moved from the primary issue queue to the secondary issue queue if instruction is dependent upon results from another instruction. In one embodiment, the instruction may be moved from the primary issue queue to the secondary issue queue after issuing the instruction for execution. In this embodiment, the instruction may be maintained in the secondary issue queue for a specified duration. Thereafter, the secondary issue queue entry containing the instruction is deallocated if the instruction has not been rejected. This patent is incorporated herein in its entirety.
U.S. Pat. No. 7,822,948 titled: “Apparatus, system, and method for discontiguous multiple issue of instructions” by Russell Lee Lewis and assigned to IBM, filed Jan. 3, 2008 teaches discontiguous multiple issue of instructions. An assignment unit assigns a plurality of instruction blocks to a plurality of issue units. The plurality of issue units each comprises a renaming map that maps each architecturally visible register address to a rename register. Each issue unit maps each architecturally visible register in the decoded instruction to a register placeholder if the renaming map entry for that architecturally visible register is invalid else maps the architecturally visible register in the decoded instruction to a rename register if the rename register entry is valid. Each issue unit further receives predecessor mapping information from the renaming map of the issue unit's predecessor issue unit in response to the assignment unit identifying a relationship with the predecessor issue unit and the final mapping information being available from the predecessor issue unit. This patent is incorporated herein in its entirety.